| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 90 === Modern microprocessor architectures are designed to employ multiple execution units that are capable of executing several instructions in parallel. The efficiency of such architectures is highly dependent on the instruction-level parallelism (ILP) that they can extract from a program. The design of an excellent value predictor becomes more important to deliver the potential performance of a widely issued, deeply-pipelined microarchitecture.
A major problem for ILP is the presence of data dependences, which prevent the execution of instructions in parallel. If an instruction is data dependent on a preceding instruction, then it can be executed only after the preceding instruction's result becomes available. If we can decide what data is available for the following
instruction, some memory cycles can be saved, and the network performance will be uplifted accordingly.
Our research focuses on improving the accuracy of the value prediction in order to raise the performance of processors. We find that both locality and loops affect data values to a certain degree. Some previous prediction schemes, such as the last predictor, stride predictor, two level predictor, hybrid predictor and FCM, have been proposed but are unable to provide desirable prediction accuracy for a high performance processor or involves too much cost. Therefore, we propose an advanced value prediction scheme able to improve the overall prediction accuracy at reasonable cost by using locality and loop property of data values.
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