Design of Fully Integrated CMOS Phase-Locked Loop with Gm-c Filter

• Main Authors: ChingTsao Chen, 陳慶造
• Other Authors: Wen-Ching Chang
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/79261550248528273563

碩士 === 淡江大學 === 電機工程學系 === 90 === Because of the process technology has developed rapidly and undergone an incredible development in recent years. Many devices such as microprocessors and communication chips were required to increase their operation frequency. We need a PLL to generate a high frequency reference clock. This thesis is introduced the design and implementation of COMS PLL. This thesis describes a transconductance-C (Gm-C) filter applies on the PLL (Phase-Locked Loop), and implement a fully integrated circuit. This thesis is divided into two parts. The first part is chapter 2, in which the operation mechanisms and related analysis of the phase-locked loop are presented. The second part is chapter 3 and chapter 4, we describe some type of the Gm-C filter and the design of the third-order lowpass Gm-C filter. Finally, chapter 4 presents the third-order lowpass Gm-C filter applied on the PLL, and circuit design of the PLL. In chapter 2 of this thesis, PLL frequency synthesizers will be introduced. And this system contains phase frequency detector, charge pump, voltage controlled oscillator, loop filter and frequency divider.Chapter 3 presents several Gm-C filters, including first-order, second- order and third-order Gm-C lowpass filter. In chapter 4, we employ active element to achieve third-order low-pass filter and apply on the PLL. The PLL was realized in a 0.5μm CMOS technology, operation frequency is 471MHz, and the core circuit dissipates 150mW from a 5-V power supply.