| Summary: | 碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 90 === Recently, the related researches report that the Discrete Wavelet Transform (DWT) can achieve outstanding compression ratio with subjectively pleasing images at low bit-rate. It’s adopted in novel standards for image and video compression, such as JPEG-2000 and MPEG-4.
In this thesis, we devise the VLSI architectures and single-chip implementations for 1-D and 2-D DWT. In the 1-D DWT study, we present a reversible design of an efficient systolic architecture which can perform both Forward and Inverse DWT (IDWT). We use the same processors and storage elements in both DWT and IDWT to reduce the hardware cost. This architecture is easily scaled up with number of filter length and octaves. In the 2-D DWT study, we adopt the non-separable approach that is based on the Semi-Pyramid Algorithm. The decomposition scheme is line by line. According to the regular schedule through the levels, the RAM banks are used to save the output coefficients after decomposition. This architecture use less memory and processors than other designs. Also, we propose a separable approach. The coefficient folding decimation filters are used in horizontal decomposition at first stage and second stage uses the parallel filters to decompose in vertical. Thus, we can devise a low memory and high efficiency architecture for 2-D DWT without transposition storage.
Finally, the chips are implemented by using the 0.35μm 1P4M CMOS technology. Experimentally, the reversible 1-D DWT chip can work at 83MHz and the power consumption is 182mW. The non-separable implementation of 2-D DWT chip can work at 62MHz and the power consumption is 351mW.
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