A Sigma-Delta Modulator and Demodulator for Speech Codec Systems

碩士 === 南台科技大學 === 電子工程系 === 90 === In this thesis, a Sigma-Delta modulator (SDM) and a Sigma-Delta demodulator (SDDM) for a speech codec system are proposed. Basically, the switched-capacitor (SC) technique and the switched-current (SI) technique can be used to implement SDMs. In this the...

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Main Authors: Wei-Zen Su, 蘇威仁
Other Authors: Shuenn Yuh Lee
Format: Others
Language:en_US
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/06506326080543086770
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spelling ndltd-TW-090STUT04280152016-11-22T04:12:48Z http://ndltd.ncl.edu.tw/handle/06506326080543086770 A Sigma-Delta Modulator and Demodulator for Speech Codec Systems 應用於語音系統之三角積分調變器與解調變器 Wei-Zen Su 蘇威仁 碩士 南台科技大學 電子工程系 90 In this thesis, a Sigma-Delta modulator (SDM) and a Sigma-Delta demodulator (SDDM) for a speech codec system are proposed. Basically, the switched-capacitor (SC) technique and the switched-current (SI) technique can be used to implement SDMs. In this thesis, the SI technique is employed. With the SI technique, the signal processing blocks including anti-aliasing filter, ADC, DAC, reconstruction filter and logic circuits can be integrated by a standard digital CMOS process. The advantages are not only easier designed and integrated with other parts in a mixed-mode system but also lower cost than the SC technique. Besides, it is beneficial to the low voltage and low power applications. However, the encountered problem is the performance far away from the SC technique. The main reason is that the non-ideal effects will degrade the performance of SI systems. Thus, a high performance SI memory cell is needed for SI circuits and systems. By taking into account the non-ideal effects, we develop a novel switched-current class AB memory cell and apply it on an SDM. Our memory cell has the advantages of high input dynamic range, high linearity, signal-independent settling behavior, and low power consumption. The proposed SDM is simulated with the TSMC 0.35μm 1P4M standard CMOS technology. Simulation results show that the SDM has a peak signal-to-noise plus distortion ratio (PSNDR) of 69dB, the power consumption is 0.52mW, and the dynamic range is 70dB with a single 2.5V power supply. As to the Sigma-Delta demodulator (SDDM), it is a third-order SDDM. It encodes a 18-bit input to a 1-bit output at a clock rate of 512 kHz i.e. the oversampling ratio (OSR) is equal to 64. It has a peak-signal-to-noise-ratio (PSNR) of 82dB. Both of the proposed SDM and SDDM are applicable to the speech codec systems with a 10-bit resolution. Shuenn Yuh Lee 李順裕 2002 學位論文 ; thesis 70 en_US
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description 碩士 === 南台科技大學 === 電子工程系 === 90 === In this thesis, a Sigma-Delta modulator (SDM) and a Sigma-Delta demodulator (SDDM) for a speech codec system are proposed. Basically, the switched-capacitor (SC) technique and the switched-current (SI) technique can be used to implement SDMs. In this thesis, the SI technique is employed. With the SI technique, the signal processing blocks including anti-aliasing filter, ADC, DAC, reconstruction filter and logic circuits can be integrated by a standard digital CMOS process. The advantages are not only easier designed and integrated with other parts in a mixed-mode system but also lower cost than the SC technique. Besides, it is beneficial to the low voltage and low power applications. However, the encountered problem is the performance far away from the SC technique. The main reason is that the non-ideal effects will degrade the performance of SI systems. Thus, a high performance SI memory cell is needed for SI circuits and systems. By taking into account the non-ideal effects, we develop a novel switched-current class AB memory cell and apply it on an SDM. Our memory cell has the advantages of high input dynamic range, high linearity, signal-independent settling behavior, and low power consumption. The proposed SDM is simulated with the TSMC 0.35μm 1P4M standard CMOS technology. Simulation results show that the SDM has a peak signal-to-noise plus distortion ratio (PSNDR) of 69dB, the power consumption is 0.52mW, and the dynamic range is 70dB with a single 2.5V power supply. As to the Sigma-Delta demodulator (SDDM), it is a third-order SDDM. It encodes a 18-bit input to a 1-bit output at a clock rate of 512 kHz i.e. the oversampling ratio (OSR) is equal to 64. It has a peak-signal-to-noise-ratio (PSNR) of 82dB. Both of the proposed SDM and SDDM are applicable to the speech codec systems with a 10-bit resolution.
author2 Shuenn Yuh Lee
author_facet Shuenn Yuh Lee
Wei-Zen Su
蘇威仁
author Wei-Zen Su
蘇威仁
spellingShingle Wei-Zen Su
蘇威仁
A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
author_sort Wei-Zen Su
title A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
title_short A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
title_full A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
title_fullStr A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
title_full_unstemmed A Sigma-Delta Modulator and Demodulator for Speech Codec Systems
title_sort sigma-delta modulator and demodulator for speech codec systems
publishDate 2002
url http://ndltd.ncl.edu.tw/handle/06506326080543086770
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