| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 90 === With the huge bandwidth (i.e., the data transmission rate) available from optical fiber, the performance bottleneck of ATM-based broadband network has shifted from data transmission rate to processing power of ATM switches and propagation delay of transmission media. With the stochastic nature of input traffic, buffering is an indispensable element of all ATM switches. Although due to the head-of-line effect the throughput with input buffering is significantly lower than that with output buffering, output buffering implies higher complexity. To balance the performance and complexity issues, it is proposed to study nonblocking ATM switches with input/output buffers. The traditional performance measures of ATM switches are cell-based. For many applications the data unit, e.g., a video frame, is too large to place into an ATM cell, and thus is segmented into a series of cells. Thus, contiguous ATM cells are strongly correlated in the sense that they are destined for the same destination or the same ATM switch output. Burst-level performance measures of many applications that generate bursty traffic could more closely reflect quality of service. Therefore we will study both burst and cell level performance measures, e.g., burst (cell) average delay. In addition, since real-time information (e.g., voice, video, and multimedia) has been and expectedly will be the main stream of network traffic, their special requirements should be taken into account while designing ATM switches. One common feature of real-time information is that delay constraint is tight but burst (cell) loss under a certain level is allowed. In other words, bursts (cells) beyond a certain delay constraint might as well be discarded. Thus, it is proposed to analyze another type of performance measure: burst (cell) loss probability caused by excessive delay. In addition, since the priority of real-time traffic is usually higher than that of non-real-time traffic, the priority of each input port is classified into high or low priority. We will employ appropriate priority control to provide different burst (cell) average delays and delay loss probabilities to traffic with different priorities. Lastly, it is proposed to study the effects of the following factors on the design of ATM switches: high and low priority average burst length, high priority input port ratio, unbalanced pattern of traffic, number of input ports, and speed-up and cell contention resolution scheme (priority vs. random) of switches.
|
|---|
