8-bit, High Conversion Rate Pipelined ADC with Improved Capacitors
碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === The two channels of 8-bit 125MSPS pipelined ADC with the different kinds of capacitors were implemented in a single chip. The applications of this ADC are focused on the high resolution LCD controller and the Gigabit-Ethernet physical layer. All analo...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88671675775857931403 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === The two channels of 8-bit 125MSPS pipelined ADC with the different kinds of capacitors were implemented in a single chip. The applications of this ADC are focused on the high resolution LCD controller and the Gigabit-Ethernet physical layer. All analog circuits are fully differential with a 2Vpp input signal and a 3.3V power supply. This chip has been designed, laid out, fabricated, and tested completely.
The two ADC channels with the different kinds of capacitors are operated separately. It is useful to demonstrate that the proposed lateral-interlaced capacitor has better matching and smaller area than the traditional metal-to-metal-sandwich capacitor when the mismatches occurred.
The total chip area is 2.2 x 3 mm2 in TSMC 0.35um 1P4M CMOS logic silicide technology. The measured performance included a peak SNDR about 47dB at low conversion rate (<62.5MHz) and 35dB at high conversion rate (>62.5MHz). The power dissipation at the maximum conversion rate (125MHz) is 204.5mW.
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