Design and Implementation of JPEG2000 EBCOT coder

碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === JPEG2000 system is the newest standard for still image compression. In this Thesis, we discuss the basic architecture of JPEG2000 system, which could be viewed as an evolution of image compression techniques during recent years. However, the key compo...

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Main Authors: CHUN-AN CHYAN, 簡崇安
Other Authors: Sao-Jie Chen
Format: Others
Language:en_US
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/44684953777007916715
id ndltd-TW-090NTU00442068
record_format oai_dc
spelling ndltd-TW-090NTU004420682015-10-13T14:38:19Z http://ndltd.ncl.edu.tw/handle/44684953777007916715 Design and Implementation of JPEG2000 EBCOT coder JPEG2000方塊編碼器之設計與實作 CHUN-AN CHYAN 簡崇安 碩士 國立臺灣大學 電機工程學研究所 90 JPEG2000 system is the newest standard for still image compression. In this Thesis, we discuss the basic architecture of JPEG2000 system, which could be viewed as an evolution of image compression techniques during recent years. However, the key component, which is called “EBCOT,” contains many bit-level computation and multiple scan, it makes JPEG2000 too slow to fit some applications if we use general purpose CPU to execute JPEG2000. We design and implement an ASIC to accrete EBCOT, the cycles needed are reduced to about 45% of the original algorithm, and the clock rate can reach 133MHz in our simulation. Sao-Jie Chen 陳少傑 2002 學位論文 ; thesis 73 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === JPEG2000 system is the newest standard for still image compression. In this Thesis, we discuss the basic architecture of JPEG2000 system, which could be viewed as an evolution of image compression techniques during recent years. However, the key component, which is called “EBCOT,” contains many bit-level computation and multiple scan, it makes JPEG2000 too slow to fit some applications if we use general purpose CPU to execute JPEG2000. We design and implement an ASIC to accrete EBCOT, the cycles needed are reduced to about 45% of the original algorithm, and the clock rate can reach 133MHz in our simulation.
author2 Sao-Jie Chen
author_facet Sao-Jie Chen
CHUN-AN CHYAN
簡崇安
author CHUN-AN CHYAN
簡崇安
spellingShingle CHUN-AN CHYAN
簡崇安
Design and Implementation of JPEG2000 EBCOT coder
author_sort CHUN-AN CHYAN
title Design and Implementation of JPEG2000 EBCOT coder
title_short Design and Implementation of JPEG2000 EBCOT coder
title_full Design and Implementation of JPEG2000 EBCOT coder
title_fullStr Design and Implementation of JPEG2000 EBCOT coder
title_full_unstemmed Design and Implementation of JPEG2000 EBCOT coder
title_sort design and implementation of jpeg2000 ebcot coder
publishDate 2002
url http://ndltd.ncl.edu.tw/handle/44684953777007916715
work_keys_str_mv AT chunanchyan designandimplementationofjpeg2000ebcotcoder
AT jiǎnchóngān designandimplementationofjpeg2000ebcotcoder
AT chunanchyan jpeg2000fāngkuàibiānmǎqìzhīshèjìyǔshízuò
AT jiǎnchóngān jpeg2000fāngkuàibiānmǎqìzhīshèjìyǔshízuò
_version_ 1717755688532312064