CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System

碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === This thesis introduces power detected type feedback control IF/Baseband automatic gain control system (AGC) for CDMA based IS-95 communication system. This system covers wide dynamic range input signals and is robust against phase error caused by comm...

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Main Authors: Bay Shin Lien, 連倍興
Other Authors: Chorng Kuang Wang
Format: Others
Language:zh-TW
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/27387007350586717879
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spelling ndltd-TW-090NTU004420582015-10-13T14:38:19Z http://ndltd.ncl.edu.tw/handle/27387007350586717879 CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System 適用於IS-95通訊系統之CMOS中頻/基頻類比信號處理器 Bay Shin Lien 連倍興 碩士 國立臺灣大學 電機工程學研究所 90 This thesis introduces power detected type feedback control IF/Baseband automatic gain control system (AGC) for CDMA based IS-95 communication system. This system covers wide dynamic range input signals and is robust against phase error caused by communication channel with rapid system settling time. Various amplitude architectures are discussed and compared with the issues of yield cost, stability and responding time. From these points of view, feedback control type AGC takes advantages over stability and cost issues and by using power detection mechanism, the AGC system can be robust against phase error caused by severe channel environment. With enough loop bandwidth, the close loop AGC system can accommodate rapid fading channel and settles within required timing specifications. In the aspects of circuit design, a new quadrature wave shaping buffer architecture and squaring-summing circuit as a power detector are proposed. The I/Q wave shaping buffer can generate exact 90° quadrature output signals and gains 12dB more phase noise response for the oscillator due to its architecture characteristics. The power detector is designed by employing MOS inherent I-V characteristics and thus no individual squaring and summing blocks are needed for the input complex signals. The circuits, i.e. VGA, mixer, ring oscillator, 7th-order Chebyshev low pass filter, output wideband amplifier, loop filter, and opamp based integrator are implemented to consist of the AGC system. At last, the circuits of the AGC system are verified from the post-layout simulation results. This chip is fabricated by 0.35mm 1P4M TSMC CMOS technology. The chip occupies 1380mm´1380mm yield area and consumes 24mW under 2V power supply. Chorng Kuang Wang 汪重光 2002 學位論文 ; thesis 101 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === This thesis introduces power detected type feedback control IF/Baseband automatic gain control system (AGC) for CDMA based IS-95 communication system. This system covers wide dynamic range input signals and is robust against phase error caused by communication channel with rapid system settling time. Various amplitude architectures are discussed and compared with the issues of yield cost, stability and responding time. From these points of view, feedback control type AGC takes advantages over stability and cost issues and by using power detection mechanism, the AGC system can be robust against phase error caused by severe channel environment. With enough loop bandwidth, the close loop AGC system can accommodate rapid fading channel and settles within required timing specifications. In the aspects of circuit design, a new quadrature wave shaping buffer architecture and squaring-summing circuit as a power detector are proposed. The I/Q wave shaping buffer can generate exact 90° quadrature output signals and gains 12dB more phase noise response for the oscillator due to its architecture characteristics. The power detector is designed by employing MOS inherent I-V characteristics and thus no individual squaring and summing blocks are needed for the input complex signals. The circuits, i.e. VGA, mixer, ring oscillator, 7th-order Chebyshev low pass filter, output wideband amplifier, loop filter, and opamp based integrator are implemented to consist of the AGC system. At last, the circuits of the AGC system are verified from the post-layout simulation results. This chip is fabricated by 0.35mm 1P4M TSMC CMOS technology. The chip occupies 1380mm´1380mm yield area and consumes 24mW under 2V power supply.
author2 Chorng Kuang Wang
author_facet Chorng Kuang Wang
Bay Shin Lien
連倍興
author Bay Shin Lien
連倍興
spellingShingle Bay Shin Lien
連倍興
CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
author_sort Bay Shin Lien
title CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
title_short CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
title_full CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
title_fullStr CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
title_full_unstemmed CMOS IF/Baseband Analog Signal Processor for CDMA based IS-95 Communication System
title_sort cmos if/baseband analog signal processor for cdma based is-95 communication system
publishDate 2002
url http://ndltd.ncl.edu.tw/handle/27387007350586717879
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