Design of A PLL with Fast-Lock and Low Jitter

碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === In this thesis, a methodology is applied to design a fast lock phase lock loop and programmable phase bandwidth. The complete design flow is presented from the system level specification to layout and measurement result. This high level system is described using...

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Bibliographic Details
Main Authors:	SHAO-KU KAO, 高少谷
Other Authors:	Shen-Iuan Liu
Format:	Others
Language:	zh-TW
Published:	2002
Online Access:	http://ndltd.ncl.edu.tw/handle/10837112042140208613

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spelling	ndltd-TW-090NTU004420272015-10-13T14:38:19Z http://ndltd.ncl.edu.tw/handle/10837112042140208613 Design of A PLL with Fast-Lock and Low Jitter 具快速鎖定與低抖動鎖相迴路之設計 SHAO-KU KAO 高少谷碩士國立臺灣大學電機工程學研究所 90 In this thesis, a methodology is applied to design a fast lock phase lock loop and programmable phase bandwidth. The complete design flow is presented from the system level specification to layout and measurement result. This high level system is described using behavioral models. Behavioral model is to verify the system before down to the circuit level. This can reduce the simulation time in Hspice. The final layout is extracted and the system performance is measured. Shen-Iuan Liu 劉深淵 2002 學位論文 ; thesis 66 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === In this thesis, a methodology is applied to design a fast lock phase lock loop and programmable phase bandwidth. The complete design flow is presented from the system level specification to layout and measurement result. This high level system is described using behavioral models. Behavioral model is to verify the system before down to the circuit level. This can reduce the simulation time in Hspice. The final layout is extracted and the system performance is measured.
author2	Shen-Iuan Liu
author_facet	Shen-Iuan Liu SHAO-KU KAO 高少谷
author	SHAO-KU KAO 高少谷
spellingShingle	SHAO-KU KAO 高少谷 Design of A PLL with Fast-Lock and Low Jitter
author_sort	SHAO-KU KAO
title	Design of A PLL with Fast-Lock and Low Jitter
title_short	Design of A PLL with Fast-Lock and Low Jitter
title_full	Design of A PLL with Fast-Lock and Low Jitter
title_fullStr	Design of A PLL with Fast-Lock and Low Jitter
title_full_unstemmed	Design of A PLL with Fast-Lock and Low Jitter
title_sort	design of a pll with fast-lock and low jitter
publishDate	2002
url	http://ndltd.ncl.edu.tw/handle/10837112042140208613
work_keys_str_mv	AT shaokukao designofapllwithfastlockandlowjitter AT gāoshǎogǔ designofapllwithfastlockandlowjitter AT shaokukao jùkuàisùsuǒdìngyǔdīdǒudòngsuǒxiānghuílùzhīshèjì AT gāoshǎogǔ jùkuàisùsuǒdìngyǔdīdǒudòngsuǒxiānghuílùzhīshèjì
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Design of A PLL with Fast-Lock and Low Jitter

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