| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 90 === With the vigorous development of video multimedia,applications of the video domain will become popular like video telephone,e-book,digital camera.It’s convenient if we display pictures on monitor (VGA,TV) and people in public were used to it.In this thesis,we implement color video processor with VHDL in order to read data from memory and display a picture on monitor as desired on system.Furthermore ,we can choose functions to make a picture magnify,reduce,rotate and if we move the cursor to make invisible become visible.We also synthesize function module with VHDL,and replace the traditional image process handled with CPU in my investigation.By the way,we can reduce the loss of hardware resources and enhance the efficiency.One development process started with a behavioral model written inVHDL.After compilation and simulation,the behavioral model was refined into a synthesizable RTL model.Following the placement and routing of the netlist with the Altera’s Maxplus2 FPGA software,an FPGA was finally programmed.From the simulation result,it shows that the chip can operate up to 30MHz.
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