Three Stages Pipelined Analog-to-Digital Converter
碩士 === 國立海洋大學 === 電機工程學系 === 90 === In this thesis, we design a 10-bit, 20Msamples/s, three stages pipelined analog-to-digital converter（ADC）. The converter consists of 3 stages with a resolution 4-b/stage with digital error correction. There are 48 comparators and 5 operational amplifier...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91927556524315407803 |