| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 90 === In this thesis, we design a 10-bit, 20Msamples/s, three stages pipelined analog-to-digital converter（ADC）. The converter consists of 3 stages with a resolution 4-b/stage with digital error correction. There are 48 comparators and 5 operational amplifiers. The main sub-circuits of the converter are sample-and-hold, 4-bit flash ADC, 4-bit digital-to-analog converter, subtractor, gain circuit, clock generator, encoder, register, digital error correction. The sample/hold circuit is implemented with switched-capacitor techniques. Switched-capacitor requires relative accurate capacitance not absolute accurate capacitance. It is therefore much easier to be fabricated for processing technology. The simulation results show that the overall circuit of ADC has 20MHz rate and 0.5LSB integral nonlinearity. The input range of ADC is from 0.85V to 2.45V. Power supply of 3.3V is used for this ADC chip. The power dissipation of the ADC is about 280mW. Total layout area is about 1800 1800μm2. The converter is fabricated with TSMC 0.25μm 1P5M CMOS technology.
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