An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design

碩士 === 國立清華大學 === 電機工程學系 === 90 === It is a difficult task to locate the fault sites in an IC that fails manufacturing test. But knowing where the fault is helps us to find the manufacturing defect and improve the yield. A diagnosis tool can help us to shrink the suspect region and to eas...

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Main Authors: Yu-Chiun Lin, 林祐群
Other Authors: Shi-Yu Huang
Format: Others
Language:zh-TW
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/63064354003108133427
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spelling ndltd-TW-090NTHU04420452015-10-13T10:34:06Z http://ndltd.ncl.edu.tw/handle/63064354003108133427 An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design 用一種類似分群組方式的演算法來做完全掃瞄設計過之電路的多重錯誤診斷 Yu-Chiun Lin 林祐群 碩士 國立清華大學 電機工程學系 90 It is a difficult task to locate the fault sites in an IC that fails manufacturing test. But knowing where the fault is helps us to find the manufacturing defect and improve the yield. A diagnosis tool can help us to shrink the suspect region and to ease the work of the failure analysis. Several types of diagnosis methodology have been proposed. For full-scan designs with only one fault, the accuracy has been improved significantly. However, the techniques for multiple fault diagnosis remain inadequate so far. In this thesis, we investigate a multiple-fault diagnosis scheme for combinational circuits or full-scan designs. In our approach, we first target the structurally independent faults based on a concept called “prime candidates”. Then, we perform a grouping algorithm to separate the rest of the suspect region into groups, each of which requires its own single-fault diagnosis process to find one fault. Experimental results on three real designs demonstrate that this approach is able to identify more faults than previous ones. On the average, we identify 3.84 faults in only 10 signal inspections with 5 faults in the chip. Shi-Yu Huang 黃錫瑜 2002 學位論文 ; thesis 42 zh-TW
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description 碩士 === 國立清華大學 === 電機工程學系 === 90 === It is a difficult task to locate the fault sites in an IC that fails manufacturing test. But knowing where the fault is helps us to find the manufacturing defect and improve the yield. A diagnosis tool can help us to shrink the suspect region and to ease the work of the failure analysis. Several types of diagnosis methodology have been proposed. For full-scan designs with only one fault, the accuracy has been improved significantly. However, the techniques for multiple fault diagnosis remain inadequate so far. In this thesis, we investigate a multiple-fault diagnosis scheme for combinational circuits or full-scan designs. In our approach, we first target the structurally independent faults based on a concept called “prime candidates”. Then, we perform a grouping algorithm to separate the rest of the suspect region into groups, each of which requires its own single-fault diagnosis process to find one fault. Experimental results on three real designs demonstrate that this approach is able to identify more faults than previous ones. On the average, we identify 3.84 faults in only 10 signal inspections with 5 faults in the chip.
author2 Shi-Yu Huang
author_facet Shi-Yu Huang
Yu-Chiun Lin
林祐群
author Yu-Chiun Lin
林祐群
spellingShingle Yu-Chiun Lin
林祐群
An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
author_sort Yu-Chiun Lin
title An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
title_short An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
title_full An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
title_fullStr An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
title_full_unstemmed An Implicit Grouping Algorithm for Multiple Faults Diagnosis of Full-Scan Design
title_sort implicit grouping algorithm for multiple faults diagnosis of full-scan design
publishDate 2002
url http://ndltd.ncl.edu.tw/handle/63064354003108133427
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