| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 90 === While wireless local area networks (WLAN) standards in the 2.4-GHz range have recently emerged in the market, the data rates supported by such systems are limited to a few megabits per second. The demand for WLAN systems that can support data rates in excess of 20 Mb/s with very low cost and low power consumption is rapidly increasing. Hence, a number of standards, such as high-performance radio LAN Type 2 (HIPERLAN2) and 802.11a, have been defined in the 5-GHz range that allow data rates greater than 20 Mb/s, offering attractive solutions for real-time imaging, multimedia, and high-speed video applications.
In this thesis, we present the design of an integer-N frequency synthesizer for 5-GHz WLAN applications. To target realistic specifications, HIPERLAN2 is chosen as the framework. Employing an integer-N architecture, the circuit generates 5.18-5.32 GHz and 5.5-5.7GHz outputs for the whole HIPERLAN2 specification. Realized in a 0.18-μm CMOS technology, the synthesizer provides a channel spacing of 20 MHz while dissipating 27 mW from a 1.5-V supply. The VCO phase noise at 1-MHz offset is equal to—109 dBc/Hz.
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