Operator-Machine Assignment Models for Semiconductor Test Facility

• Main Authors: Lin Yi Chiech, 林怡傑
• Other Authors: 簡禎富
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/21203136672562065538

碩士 === 國立清華大學 === 工業工程與工程管理學系 === 90 === Equipment costs account for more than 70% of the capital investment in a semiconductor test facility. To improve the utilization of the test machines shares the cost of test machines to more wafers, thus decreases the unit test cost of the wafer and improves the competitive strength of a semiconductor test facility. The purpose of this thesis is to develop a algorithm to find a well-performed assignment of test machines and operators for different test product mix. Assigning multiple machines to an individual operator may cause the machine interference problem. That is, when the operator is tending a machine, another machine that needs to be tended by the operator at the same time has to stay idle and wait until the operator is available again. The idle time that caused by assigning multiple test machines to an individual operator is termed as machine interference time and is a kind of capacity loss. Machine interference time raises while decision maker assigning the test machines to operators poorly. Thus, it is an important issue to find an assignment of test machines and operators that leads to relatively better system performance. In this thesis, we apply response surface methodology and genetic algorithms together with simulation method to develop the heuristic algorithms for searching the well-performed assignment of test machine and operators. The assignments found by the heuristic algorithms that we proposed have the same system performance with the assignment decided by the experienced engineer, thus to show the validity of the heuristic algorithms and can be the decision support model for new coming engineer.