IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier

碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual thresh...

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Bibliographic Details
Main Authors:	Kuo-Long Chen, 陳國龍
Other Authors:	Chua-Chin Wang
Format:	Others
Language:	zh-TW
Published:	2002
Online Access:	http://ndltd.ncl.edu.tw/handle/89494193879693845384

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spelling	ndltd-TW-090NSYS54420342015-10-13T10:28:59Z http://ndltd.ncl.edu.tw/handle/89494193879693845384 IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier 使用具有低功率止擾器雙門檻電壓之6-電晶體靜態記憶體與可程式化鎖相迴路式倍頻器之晶片設計與實作 Kuo-Long Chen 陳國龍碩士國立中山大學電機工程學系研究所 90 Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. Ａ synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators. Chua-Chin Wang 王朝欽 2002 學位論文 ; thesis 61 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. Ａ synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.
author2	Chua-Chin Wang
author_facet	Chua-Chin Wang Kuo-Long Chen 陳國龍
author	Kuo-Long Chen 陳國龍
spellingShingle	Kuo-Long Chen 陳國龍 IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
author_sort	Kuo-Long Chen
title	IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
title_short	IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
title_full	IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
title_fullStr	IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
title_full_unstemmed	IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
title_sort	ic design and implementation of 6-t sram cell using dual threshold voltage transistors and low power quenchersand programmable pll-based frequency multiplier
publishDate	2002
url	http://ndltd.ncl.edu.tw/handle/89494193879693845384
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IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier

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