IC Design and Implementation of 6-T SRAM Cell Using Dual Threshold Voltage Transistors and Low Power Quenchersand Programmable PLL-Based Frequency Multiplier
碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual thresh...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/89494193879693845384 |
| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers.
The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. Ａ synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.
|
|---|