| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 90 ===
The objective of this thesis is to study the implementation of variable length encoding/decoding (VLC codec). We introduce four VLC codec system architecture. First one is a bit-serial VLC codec system architecture proposed by Hsia and Tseng [1]. The others are bit-parallel VLC codec system architecture proposed by Lei and Sun [2], Shieh, Lee, and Lee [3], and us, respectively. In the bit-serial architecture, the small memory space is required to store the partial prefix bits of the codewords of the symbols, but the speed of encoding/decoding is slower. In the traditional bit-parallel architecture, the large memory space is occupied to store the codewords of the entire symbols, but the speed of encoding/decoding is faster.Our proposed bit-parallel architecture utilizes the features of the grouping codewords and symbol memory mapping and applies the numerical properties of codewords and symbol addresses to complete the overall encoding/decoding procedures. We propose an efficient group searching procedure in the encoding and decoding algorithms for our implementation. And we also introduce a symbol conversion technique to reduce the memory space required to store the codeword of the symbols. However, in our proposed architecture the encoder and the decoder can share the same table memory for storing the codeword of the symbols. In addition, the speed of encoding/decoding in our proposed bit-parallel architecture is faster than that in the PLA-based bit-parallel architecture proposed by Lei and Sun.
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