Design and Implementation of an Asynchronous AES Encryption/Decryption Chip

• Main Authors: Li-Chung Tung, 董力中
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/90903697099582779167

碩士 === 國立東華大學 === 資訊工程學系 === 90 === When people transmit information over data network, hackers may attack it. Hence, the security of information is a critical issue. National Bureau of Standards (NBS) announce the Data Encryption Standard (DES) as the encryption scheme in 1977. As technology advances, the computer operates faster and faster. The DES is no longer a safe scheme security. Due to this, Rijndael is selected as the Advanced Encryption Standard (AES) in 2000 by NIST. Rijndael is a symmetric block cipher, and it allows scalable block length and the key length is 128, 192 and 256 bits. It has the properties of simplicity, high speed and proper security. To realize an AES cipher, low power and high performance are essential design issues. This thesis presents design for the AES cipher. We combine encryption and decryption in a single chip. The design of our AES cipher uses the asynchronous architecture and micropipeline technology. There is no clock in our circuit. We use the signals request and acknowledge to control the data path instead. Since the design does not need the clock, there is no problem for generation clock tree or clock skew in a VLSI chip. Power also can be reduced since there is almost no power consumption generated by clock switch. The pipeline design allows the chip to process more data at the same time, and hence the throughput of the cipher is increased. We have implemented the design in a VLSI chip. The chip size is 5.36 mm x 5.36 mm, and the gate count is 51 K with 36 256x8 ROM and four 16x32 RAM. The throughput is 1.16 Gbit/s and the power dissipation is 474 mW. Our results show that the design is feasible and achieves good performance.