Low power Turbo decoder for communication system

碩士 === 國立中央大學 === 電機工程研究所 === 90 === Turbo codes, proposed by Berrou et al. in 1993, which are parallel concatenated convolution codes joined through interleavers. Iterative decoding techniques are used for decoding. It has been shown that any decoder that accepts soft inputs (include a priori valu...

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Bibliographic Details
Main Authors: Nai-Hsuan Hsueh, 薛乃軒
Other Authors: none
Format: Others
Language:zh-TW
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/65858756492959214033
Description
Summary:碩士 === 國立中央大學 === 電機工程研究所 === 90 === Turbo codes, proposed by Berrou et al. in 1993, which are parallel concatenated convolution codes joined through interleavers. Iterative decoding techniques are used for decoding. It has been shown that any decoder that accepts soft inputs (include a priori values) and generates soft outputs can be used for iterative decoding. Turbo code can achieve almost near Shannon limit error correction performance, its powerful error correcting capability is very attractive for mobile wireless applications to combat channel fading. Turbo code has been adopted as the channel coding schemes for the services of high transmission rates in a number of the 3rd generation mobile systems (3GPP), such as WCDMA and CDMA2000. In this thesis, we focus on the realization of the soft-input and soft-output comment decoder. The operating algorithm of Turbo code decoder is much complicated than the conventional convolutional decoder, and there are several implementation issues. There are several algorithms that meet the requirements of the soft-input and soft-output structure. A Soft-Output Viterbi Algorithm (SOVA) proposed by Hagenauer is used to implement the soft-input and soft-output convolutional decoder. In realization, we first discuss the proposed architecture and the implementation issues. Then, the encoding/decoding process is simulated by Matlab program and verified by Verilog HDL. Finally, the architecture of the SOVA decoder is then mapped on circuit design, and the layout implementation is made by using TSMC standard cell and 0.35μm TSMC CMOS SPDM technology.