Multi-module synchronization methodology

• Main Authors: Shi-Dai Mai, 麥世達
• Other Authors: Chau-Chin Su
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/87439973477563177753

碩士 === 國立中央大學 === 電機工程研究所 === 90 === In this thesis, we propose two novel multi-module synchronization mechanisms. The first architecture describes a board level multiple modules synchronization. The second architecture describes an on-chip multiple modules synchronization. The two techniques target the synchronization for test channels in automatic test equipment (ATE) and system on a chip (SOC) environment respectively. We utilize fine tune mechanisms to suppress timing skews between modules and provide the highly stable phase. Both multi-module synchronization are based on TSMC 0.35 µm 1P4M CMOS and TSMC 0.18 µm 1P6M CMOS processes respectively. The results are at 200MHz and 1GHz respectively. The measurement and simulation results show that on-board architecture is capable of reducing the skew of the five modules to less than 100ps and the clock frequency up to 200MHz with 50ps clock jitter when the initial skew of each module is as large as 800ps. The simulation results also show that on-chip architecture reduces the skew of the five modules to less than 80ps and the clock frequency up to 1GHz with 20ps clock jitter when the initial skew of each module is as large as 800ps