| Summary: | 碩士 === 國立交通大學 === 電資學院學程碩士班 === 90 === A timing generator (TG) is the most important part on the tester timing control system. It is the key factor for speeding up tester's cycle rate. Here, This research uses an alternative way to build our tester timing generator. It is different from the traditional methodology, and they used to build timing generator by current steering DAC, capacitor and comparator. In this thesis, it uses a phase locked loop to multiply the input clock rate by 4, and then use a delay locked loop to divide the clock period into 4 equal sections again. The PLL and DLL simulation have been accomplished by using lower level and lower cost technology, TSMC .6U CMOS technology. Its performance could have PLL output 400MHZ clock, and the DLL output minimum stable phase delay reach 0.625ns. 0.625ns is the minimum resolution to a tester's timing generator. We could use this circuit to supply 100MHZ data rate on a tester's TG. This methodology uses extern clock to adjust PLL and DLL output. They both used the feedback loop to control their output. So the immunity to the deviation of power supply and temperature is better than the traditional design. Although its resolution is larger, its' accuracy is still better, typical RMS accuracy < 3ps.
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