| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系 === 90 === The compressing standard on audio and video signals, such as JPEG or MPEG, includes the function of Huffman decoder. Decoding Huffman code is difficult because of the inherent property of varying code length. Existing algorithms for Huffman decoder are developed based on the data structure of Huffman codes. Using a new perspective to treat the Huffman code as a numerical sequence, we have designed a new Huffman decoder, referred to as the numerical Huffman decoder, which, compared with existing algorithms, has a better performance on decoding speed and realization complexity. This thesis proposes a hardware architecture to realize the numerical Huffman decoder. We aims to develop a hardware Huffman decoder for Huffman codes of 16-bits maximum length. The major hardware includes an adder and a shift-register,
along with five multiplexers and twelve registers. Besides, we have followed the ASIC design flow to present an IC for the Huffman decoder.
Finally, the decoding function is verified by combining the hardware decoder with printer-port transmission in an FPGA board.
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