The Fast Lock ADDLL System Uses Asynchronous Time Mapping Tracking (ATMT)

• Main Authors: Pi-Lin Lo, 羅丕霖
• Other Authors: Jin-Chern Chiou
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/00873638561030171885

碩士 === 國立交通大學 === 電機與控制工程系 === 90 === Clock skew is an increasing concern for high speed circuit designing. This paper describes a simple concept for realizing a fast all digital delay locked loop (ADDLL) circuit that operates at high frequency between 300Mhz and 800MHz and with fast lock time about 10 cycles. This ADDLL Circuit adopts a search method, called Asynchronous Time Mapping Tracking (ATMT), to detect and get the information of the phase error between the input and output clock and furthermore tune the output delay path for phase compensation. The ADDLL circuits designed in the paper are consisted of five primary parts : A. Feedback clock phase error generator : This part of the ADDLL system connected with feedback clock and generates 32 phase error outputs which has about 100ps between each other. B. Time sampling and positive edge detector : The 32 phase error outputs feed through this part and the circuit would use the positive edge of the reference clock to sample the state of each phase error. C. Phase error compensation decoder : After the phase error between the feedback clock and reference clock have been quantified , the decoder transfers the decimal data to 5 bits binary form used to control the delay line. D. 5 bits digital controlled delay line : The binary data of the compensation decoder connected with the control ports of this delay line to determine how much the delay time have to been inserted between reference and feedback clock to synchronize the clock. E. Frequency divider and system controller : The system controller is based on a phase detector(PD) has two major function, determining the data capture signal of digital delay line provided by frequency divider, and detecting the phase lock situation of the system to switch the modes of the ADDLL system. The new methodology of the ADDLL system designing in this paper successfully shortens the locked cycles of the circuit and eliminates the affection of interconnect manufacturing variations with wire RC loading affects timing performance. Key words：clock skew, ADDLL, ATMT.