On-Chip Jitter Measurement for Phase-Locked Loops

• Main Authors: Chin-Cheng Tsai, 蔡進成
• Other Authors: Prof. Chung-Len Lee
• Format: Others
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/25059466475654086878

碩士 === 國立交通大學 === 電子工程系 === 90 === Phase-Locked Loops (PLL) are used in many high-speed electronic systems. It can be employed as the clock recovery and the frequency synthesizer. Jitter is an important parameter in Phase-Locked Loops specifications. It can be defined as the deviations in a clock output transition from their ideal position. The deviation can either be leading or lagging the ideal position. In a communication system, a larger jitter affects data correctness. And in a microprocessor system, a larger jitter results in wrong computation. For the jitter measurement, we need a high-resolution (pico-second) instrument in the Automation Test Equipment (ATE) to acquire more accurate values. In the thesis, we propose a simple, built in the circuit under test, design to transfer timing difference to the digital signal. Jitter values are obtained from several digital words. As a result, a general logic ATE can do the jitter measurement and the cost of test can be reduced. This design can also be used in an SOC design to measure jitter.