Design and Generation of Coprocessing Datapath

• Main Authors: Tzung-Shian Yang, 楊宗憲
• Other Authors: Chein-Wei Jen
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/84312949795410457350

碩士 === 國立交通大學 === 電子工程系 === 90 === Embedded systems are trending toward programmable solutions to meet the time-to-market (TTM) requirements under unstable and changing standards. Technology improvement and architecture innovation drive the microprocessor performance continuously to sustain the complex multimedia applications. Novel products that support new standards require extremely high performance and cannot be power- and cost-efficient, especially for battery-powered and portable devices. For years, the industry uses the heterogeneous approach to solve this problem, which attaches specific hardware accelerators to the host embedded processor. Pre-designed and verified IP modules can significantly reduce the development time. But the hardware IP seldom meets the application requirements. Even if the developer designs his/her accelerator from scratch, some over-design is required to make the hardware re-usable. Besides, the hardware/software interface is tedious and error-prone. These motivate a coprocessing datapath generator, which synthesizes a customized hardware accelerator with the interface modules. We propose a DSP datapath generator in this thesis, which accepts the user-specified constraints to generate synthesizable Verilog code for an optimal hardware accelerator. For the specified speed requirement, the generator minimizes the number of concurrent functional units to reduce the cost. MIN (Multi-stage Interconnection Network) is adopted in this thesis as the interconnection template for large-scale accelerators to reduce the routing complexity and the silicon area in conventional MUX (multiplexor)-based architectures. The generated DSP datapath is wrapped in AMBA AHB with the auto-generated software driver, which facilitates the integration into standard platforms (e.g. several commercial ARM or PowerPC-powered hardware platforms). The generation of DCT, FFT, and DWT accelerators is available in the “Example” chapter with a complete accelerated JPEG encoder system.