Design and Implementation of A Scalable Fast Fourier Transform Core

• Main Authors: Cheng-Han Sung, 宋承翰
• Other Authors: Chein-Wei Jen
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/32927976299897019655

碩士 === 國立交通大學 === 電子工程系 === 90 === For the speed requirement of existing communication standards that adopt OFDM technique, we should employee two processing elements in single PE architecture in FFT module, which will induce the requirement of accessing four data in the same cycle from the memory. Employing multiple-port memory will cause redundant power dissipation consume a lot of silicon area. In our thesis, we derive non-conflicting data format that can be adopted to replace single multiple-port memory to multiple single-port memories to achieve the purpose of low area cost and low power dissipation. Besides deriving non-conflicting data format, we also propose an equation to descript the non-conflicting data format from the hardware points of view. By using our equation, we can implement the function without redundant hardware cost. The successful implement for translating single multiple-port memory to multiple single-port memories will require two things. One is non-conflicting data format, the other is a suitable address generator. In our thesis, we propose our address-generating scheme that can generate four addresses easily from simple counter value. Besides the requirement of addresses of fixed length FFT, we also develop scalable-length ability in our address-generating scheme. Using ROM to indicate when and where we perform twiddle factor is not a feasible method, thus we propose a mechanism that can predict the position and the value of twiddle factor to replace a lot of silicon of ROM. Different speed requirement will induce different number of port of memory. For the different speed requirement, we also propose a method that can handle the ports that is power of two. In our method, we only need one set of address generator to handle the speed requirement that needs power of two ports without modifying the concept of original address generator of IRDA. FFT module is a power-consuming product, hence we hope to high-level estimate the power dissipation in the beginning of design. In our thesis, we propose the high-level power model to describe the power dissipation that focus on the power dissipation of memory partition. From our power model, we can see that the power dissipation of single multiple-port memory can be reduced by replacing single multiple-port memory to multiple singe-port memories dramatically.