The Application of Semiconductor Heterostructures in Cooling Chips
碩士 === 國立交通大學 === 電子工程系 === 90 === The purpose to this thesis is mainly to develop a sort of new cooling chips, fabricated with the quantum well structures of III-V compound semiconductor and called “Thermionic coolers”. There is a better cooling performance for thermionic coolers than that for conv...
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ndltd-TW-090NCTU04280422015-10-13T10:04:50Z http://ndltd.ncl.edu.tw/handle/95462741634237014642 The Application of Semiconductor Heterostructures in Cooling Chips 異質接面半導體致冷器上之應用 Tien-Cheng Lee 李天成 碩士 國立交通大學 電子工程系 90 The purpose to this thesis is mainly to develop a sort of new cooling chips, fabricated with the quantum well structures of III-V compound semiconductor and called “Thermionic coolers”. There is a better cooling performance for thermionic coolers than that for conventional thermoelectric coolers. This thesis is divided into three parts. Firstly we introduce the operation principle of a thermoelectric cooler and some characteristic parameters about a cooler. Then we publish a new cooling idea to improve some disadvantages of the conventional TE cooler , construct a design model based on the related theorems, and apply the heterostructure quantum well semiconductor in the new field. Through the appreciate theoretical design, finally we can fabricate a cooler object and make an experiment in its cooling performance by applying a DC current bias. By comparing the cooling ability for thermionic coolers with that for thermoelectric ones, the initial design conception is verified. Through our detailed design flow, we had successfully fabricated a new cooler chip which owns better cooling performances. Its maximum cooling temperature might reach to 6.5℃under the room temperature operation circumstances, which is much better than the maximum 4℃ temperature drop for a TE cooler made by n+ GaAs substrate. Besides, we also discussed the influences of some possible factors on the device cooling ability, such as etched mesa region, operation background temperature, substrate thickness and quantum well period number, and so on. From our discussion results, we hope that we could unceasingly improve its cooling performance, stability and reliability, finally we might widely apply the micro-coolers to nano device fields. Chien-Ping Lee 李建平 2002 學位論文 ; thesis 49 zh-TW |
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碩士 === 國立交通大學 === 電子工程系 === 90 === The purpose to this thesis is mainly to develop a sort of new cooling chips, fabricated with the quantum well structures of III-V compound semiconductor and called “Thermionic coolers”. There is a better cooling performance for thermionic coolers than that for conventional thermoelectric coolers.
This thesis is divided into three parts. Firstly we introduce the operation principle of a thermoelectric cooler and some characteristic parameters about a cooler. Then we publish a new cooling idea to improve some disadvantages of the conventional TE cooler , construct a design model based on the related theorems, and apply the heterostructure quantum well semiconductor in the new field. Through the appreciate theoretical design, finally we can fabricate a cooler object and make an experiment in its cooling performance by applying a DC current bias. By comparing the cooling ability for thermionic coolers with that for thermoelectric ones, the initial design conception is verified.
Through our detailed design flow, we had successfully fabricated a new cooler chip which owns better cooling performances. Its maximum cooling temperature might reach to 6.5℃under the room temperature operation circumstances, which is much better than the maximum 4℃ temperature drop for a TE cooler made by n+ GaAs substrate. Besides, we also discussed the influences of some possible factors on the device cooling ability, such as etched mesa region, operation background temperature, substrate thickness and quantum well period number, and so on. From our discussion results, we hope that we could unceasingly improve its cooling performance, stability and reliability, finally we might widely apply the micro-coolers to nano device fields.
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author2 |
Chien-Ping Lee |
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Chien-Ping Lee Tien-Cheng Lee 李天成 |
author |
Tien-Cheng Lee 李天成 |
spellingShingle |
Tien-Cheng Lee 李天成 The Application of Semiconductor Heterostructures in Cooling Chips |
author_sort |
Tien-Cheng Lee |
title |
The Application of Semiconductor Heterostructures in Cooling Chips |
title_short |
The Application of Semiconductor Heterostructures in Cooling Chips |
title_full |
The Application of Semiconductor Heterostructures in Cooling Chips |
title_fullStr |
The Application of Semiconductor Heterostructures in Cooling Chips |
title_full_unstemmed |
The Application of Semiconductor Heterostructures in Cooling Chips |
title_sort |
application of semiconductor heterostructures in cooling chips |
publishDate |
2002 |
url |
http://ndltd.ncl.edu.tw/handle/95462741634237014642 |
work_keys_str_mv |
AT tienchenglee theapplicationofsemiconductorheterostructuresincoolingchips AT lǐtiānchéng theapplicationofsemiconductorheterostructuresincoolingchips AT tienchenglee yìzhìjiēmiànbàndǎotǐzhìlěngqìshàngzhīyīngyòng AT lǐtiānchéng yìzhìjiēmiànbàndǎotǐzhìlěngqìshàngzhīyīngyòng AT tienchenglee applicationofsemiconductorheterostructuresincoolingchips AT lǐtiānchéng applicationofsemiconductorheterostructuresincoolingchips |
_version_ |
1716826632508932096 |