Selcetion of Alternative Routing for Possibly Delayed Lots in IC Foundry

• Main Author: 林勝智
• Other Authors: 巫木誠
• Format: Others
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/97770104723451793462

碩士 === 國立交通大學 === 工業工程與管理系 === 90 === In semiconductor manufacturing, some manufacturing operations may be performed by different routes. In order to improve the on-time delivery of IC foundries, this research develops a method for the possibly delayed lots in the decision-making of changing routes. A lot is identified as a possibly delayed one whenever its progress of manufacturing is behind its lot control schedule. The lot control schedule defines the target progress of each operation of the lot. For a particular possibly delayed lot, facing the choice of two alternative routes, the lot is assigned to take the route where all the lots in the route that are possibly delayed have shorter cycle time. That is, if the lot is dispatched to a route, it may increase the cycle time of all the other lots in the route and may become possibly delayed ones. The cycle time of all these lots in a route can be computed by a method developed in this research. Simulation results show that the proposed method for changing routes can effectively improve on-time delivery when the percentage of planned delayed lots is low (10%), and cannot work well when the percentage of planned delayed lots is relatively high (15%).