| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === There are various applications of the speech synthesis system, such as TTS system, toys, electronic books, etc. For the portable speech synthesis devices, how to reduce the memory requirement is an important issue.
This paper presents a hardware architecture based on the TD-PSOLA (Time Domain Pitch Synchronous Overlap-and-Add) algorithm and the sub-syllable synthesis units. The required memory size is 277k Bytes if the sampling frequency is 8k Hz and each sample uses 8 bits. In our listening experiments, the synthesized speech is still highly understandable. As there are lots of different cosine values in the PSOLA algorithm, we adopt CORDIC algorithm to avoid the huge memory requirement. In this paper, we propose a fast CORDIC (sine & cosine mode) algorithm which is 5 times faster than the traditional CORDIC (sine & cosine mode) algorithm.
In the future work, we will focus on the multi-tone extraction and the combination of DAC.
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