A 6-Bit Flash A/D Converter with New Design Techniques
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The thesis presents a high-speed 6-bit CMOS flash ADC with new design techniques. Autozeroing technique without idle time is the most effective way to suppress the errors due to process variation for the applications of continuous input conversion. Interpolati...
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ndltd-TW-090NCKU54421352018-06-25T06:05:08Z http://ndltd.ncl.edu.tw/handle/j5shzz A 6-Bit Flash A/D Converter with New Design Techniques 一個具有新設計技術之六位元快閃式類比/數位轉換器 Chun-Wei Hsu 許浚偉 碩士 國立成功大學 電機工程學系碩博士班 90 The thesis presents a high-speed 6-bit CMOS flash ADC with new design techniques. Autozeroing technique without idle time is the most effective way to suppress the errors due to process variation for the applications of continuous input conversion. Interpolation technique can reduce the input loading and the preamplifiers' number efficiently. However, it is difficult to include autozeroing without idle time and interpolation operations in a high-speed low-latency flash ADC at the same time. In this design, New Autozeroing with Interpolation (NAI) technique is proposed to achieve the target. A switching preamplifier is provided in NAI to avoid using non-overlap control signals required by the conventional autozeroing ADCs and to eliminate the interference, caused by the high-speed autozeroing operation, at input nodes. Besides, NAI has the merit of a single-phase control to avoid the synchronous problem since the multi-phase clocks are necessary for recent published flash ADCs with autozero. While charge injection and feedthrough in NAI limit the ADC performance, capacitor averaging technique is incorporated with NAI to decrease these errors. For the use of interpolation approach, large impedance is needed to generate enough interpolation signals to overcome noise and offset errors. That causes a large RC time constant at the interpolation nodes and deteriorates the ADC speed. A technique called, Negative Impedance Compensation (NIC), is presented to solve this problem so that the ADC can thereby achieve a higher conversion rate with small RC time constant. The designed ADC is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.0x0.8 mm^2. The measurement results show that the design can achieve an operating rate of 500MHz with a SNR>30dB. The total chip draws 261mW from 2.5V power supply. Tai-Haur Kuo 郭泰豪 2002 學位論文 ; thesis 114 en_US |
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碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The thesis presents a high-speed 6-bit CMOS flash ADC
with new design techniques. Autozeroing technique without idle time is the most effective way to
suppress the errors due to process variation for the applications of continuous input conversion.
Interpolation technique can reduce the input loading and the preamplifiers' number efficiently.
However, it is difficult to include autozeroing without idle time and interpolation operations in
a high-speed low-latency flash ADC at the same time.
In this design, New Autozeroing with Interpolation (NAI) technique is proposed
to achieve the target.
A switching preamplifier is provided in NAI to
avoid using non-overlap control signals required by the conventional autozeroing ADCs and to
eliminate the
interference, caused by the high-speed autozeroing operation, at input nodes.
Besides, NAI has the merit of a single-phase control to avoid
the synchronous problem since the multi-phase clocks are
necessary for recent published flash ADCs with autozero.
While charge injection and feedthrough in NAI
limit the ADC performance, capacitor averaging technique is incorporated
with NAI to decrease these errors.
For the use of interpolation approach, large impedance is needed to generate enough
interpolation signals to overcome noise and offset errors. That causes
a large RC time constant at the interpolation nodes and deteriorates the ADC speed.
A technique called, Negative Impedance Compensation (NIC),
is presented to solve this problem so that the ADC
can thereby achieve a higher conversion rate with small RC time constant.
The designed ADC is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.0x0.8 mm^2. The measurement results show that the design can achieve an
operating rate of 500MHz with a SNR>30dB.
The total chip draws 261mW from 2.5V power supply.
|
author2 |
Tai-Haur Kuo |
author_facet |
Tai-Haur Kuo Chun-Wei Hsu 許浚偉 |
author |
Chun-Wei Hsu 許浚偉 |
spellingShingle |
Chun-Wei Hsu 許浚偉 A 6-Bit Flash A/D Converter with New Design Techniques |
author_sort |
Chun-Wei Hsu |
title |
A 6-Bit Flash A/D Converter with New Design Techniques |
title_short |
A 6-Bit Flash A/D Converter with New Design Techniques |
title_full |
A 6-Bit Flash A/D Converter with New Design Techniques |
title_fullStr |
A 6-Bit Flash A/D Converter with New Design Techniques |
title_full_unstemmed |
A 6-Bit Flash A/D Converter with New Design Techniques |
title_sort |
6-bit flash a/d converter with new design techniques |
publishDate |
2002 |
url |
http://ndltd.ncl.edu.tw/handle/j5shzz |
work_keys_str_mv |
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