| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === In this thesis, we plan to realize the MPEG-4 simple profile video compression standard on Texas Instruments TMS320C6x Digital Signal Processing (DSP) chips figured with two-channel video signals. The major research works include the video compression software realization in the C6x DSP chip and the design of two-channel video interface circuit. The performance evaluation after porting the MPEG-4 video compression software in the C6x DSP is first achieved. Based on its vulnerability, we then improve and optimize its software implementation by using C6x software pipeline programming techniques. To advance its speed, we further propose a fast VLC decoding method, which decodes two codewords at each decoding loop in C6x platform. Another important contribution to this research is that we successfully design a video input and output interface circuit, which reduces the C6x loads in capture of image data. The realized video system shows that the realized interface circuit in a FPGA chip helps the C6x to concentrate its computation power on coding tasks such that the real-time MPEG-4 coding system can be archived.
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