IP Design of Static Memory Controller for SoC Integration and Verification

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The major target of this thesis aims at developing a static memory controller (SMC) IP, as well as constructing a fundamental SoC platform by means of a common bus interface. The system platform integrates not only the SMC but also the LCD controller together...

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Bibliographic Details
Main Authors: Cheng-Hsi Hung, 洪呈熙
Other Authors: Bin-Da Liu
Format: Others
Language:zh-TW
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/z9v3nn
Description
Summary:碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The major target of this thesis aims at developing a static memory controller (SMC) IP, as well as constructing a fundamental SoC platform by means of a common bus interface. The system platform integrates not only the SMC but also the LCD controller together with DMA controller developed by SPIC laboratory. The proposed SMC resides on the system bus and takes control of the memory system on the external bus. It supports three types of memory devices, including ROM, SRAM and flash memory. For achieving great flexibility to apply on assorted system environments, the proposed design utilizes programmable registers for storing different environmental parameters. We propose an on-chip-bus (OCB) architecture referring to the AMBA specification for convenience of SoC integration. By connecting each IP onto the system bus via the wrapper, and concurrently loading the bus arbiter and address decoder, a basic SoC platform can be completely fulfilled. All of the modules within this thesis are coded with Verilog and verified on Xilinx FPGA. The proposed design can achieve the maximum operating frequency of 24.764MHz while implemented on VIRTEXE V2000EFG680 FPGA.