Low Power Testing for CMOS Logic Testing

• Main Authors: Tsung-Chu Huang, 黃宗柱
• Other Authors: Kuen-Jong Lee
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/23446931835307075746

博士 === 國立成功大學 === 電機工程學系 === 90 === The increasing transistor density and operating speed in the system-on-a-chip (SOC) era make the power dissipation during test a critical issue. This dissertation proposes four techniques to reduce the power dissipation in test application time for CMOS logic circuits. First, we propose an input control technique that employs a D-algorithm-like approach to generate a control pattern which, when applied at the primary inputs during scan operations, can minimize the switching activity of full-scan circuits. This technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show while the vector ordering and the latch ordering techniques can achieve 22.37% of average power reduction, 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques. Second, an interleaving technique is proposed to reduce the peak power of multiple scan chain based circuits during testing. A test architecture is presented which can significantly reduce the peak power by adding delay buffers among the scan chains. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51\% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed. Third, a novel token scan architecture is developed which employs the concepts of multiphase clocking, token ring and clockgating to minimize the data transitions, to alleviate the routing and skew problems, and to eliminate the broadcasting dissipation on the clock tree and scan-in data tree during scan operations. This token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains. Fourth, we observe that previously multiphase LFSR schemes have been proposed to reduce the data transitions during test and signal process. However, due to the more complex clock generator, the broadcasting input and the multiplexing output, the power reduction is actually much limited. We propose a new LFSR architecture to improve the power reduction via developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator and employing static logic gates to implement the output multiplexer. To reduce the stages of the multiphase clock generator and the area of the multiplexer, a hybrid LFSR design combining both single and multiple phase clocks is developed. From our evaluation, our architecture has 40\% more power reduction than the previous $n$-phase LFSR architecture when $n$ is greater than 27 and up to 70% power reduction compared to a conventional LFSR. In summary, the input control technique is mainly for reducing the average power dissipation while the interleaving technique is for the peak power. Both the token scan architecture and the hybrid LFSR scheme can reduce average power as well as peak power. To conclude this dissertation, we tabulate the reduction efficiency of our techniques and analyze their applicability and suitability. Based on the analysis, some future work is suggested.