Design and Application of CMOS Bulk Input Technique.

• Main Authors: Jing-Fu Lin, 林京甫
• Other Authors: Hong-Yi Huang
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/14185792789994545308

碩士 === 輔仁大學 === 電子工程學系 === 90 === In VLSI circuits, the digital circuits are the important parts in a chipset. The logic circuits occupy the almost of digital circuits. In this paper, we make a logic circuits history review. Some popular logic circuits will be introduced. Then the bulk input differential logic (BIDL) is presented. The bulk terminals of conventional circuits always connect to highest or lowest voltage. The bulk input differential logic circuits make the bulk terminals able to receive signals. It improves the logic design flexibility into a wide margin. A boost circuit is employed to the bulk terminal of the input device to avoid the p/n junction forward bias problem. The BIDL can generate a pair of complementary full-swing output signals without dc power dissipation. It is shown that the BIDL has better speed and power performance compared to the conventional differential logic circuits in simulation results. In more than two inputs logic gates, the improvement of power-delay product is more than thirteen percentages. To verify the BIDL is good as simulation results, we design a test chip. The chip is a frequency synthesizer which uses the BIDL in the prescaler design. In the prescaler, an 8-inputs BIDL gate can operate at 2GHz in TSMC 0.25um process simulation. The test chip is being fabricated.