A CMOS High-speed Voltage Comparator
碩士 === 逢甲大學 === 電機工程所 === 90 === This thesis presents a design of an innovational high-speed CMOS voltage comparator. The comparator proposed in this thesis uses a p-type differential pair as input stage to provide more gains which differs from using an n-type differential pair. Furthermore, the com...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ub99h5 |