| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 90 === Due to the coming of the system-on-chip (SoC) age, the chip design become more and more complicated. To deal with the increasing complexity, SIP modules become popular for modern chip design. Since the SIP modules in the chip have provided by different companies or departments, it is very important for the development of SoC chip to integrate all the SIP modules into a single chip. At the same time, it also makes the floorplan process of the SoC chip to become more critical than even. Consider the integration of a SoC chip, a best floorplan approach can obtain smaller chip area and better timing result. However, the performance of a better floorplan approach depends on the data representation of the floorplans.
In this paper, we present a new representation, named double -bound-list (DBL), for non-slicing floorplans. The DBL representation combines the advantages of popular representation such as sequence pair, O-tree, B*-tree, CBL, TCG, and SCP. For example, DBL conforms to the requirements of P-admissible properties. From the structure of the DBL representation, the area of the floorplan result and the geometric relationship of adjacent modules can be immediately found. In addition, the DBL representation needs less memory for the storage of non-slicing floorplans and conforms the one-to-one mapping relation between non-slicing floorplans and DBL representations.
Finally, the paper introduces how to use the DBL representation to develop a simulated-annealing-based floorplan approach. The experimental results show that the proposed approach obtain better floorplan area under less memory requirement.
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