| Summary: | 碩士 === 中華大學 === 科技管理研究所 === 90 === In this thesis, we employed the method of wafer level test with high stress voltage to accelerate the device degradation. Then, we utilized the accelerated factor to get the device lifetime that we operate under normal voltage. We found that this new method saves us 2.43 times of testing time and 3-day package time. This methodology brings us tremendous economic benefit.
Moreover, in low temperature, the Hot Carrier Induce is extremely large, so if we move our testing environment to a low temperature system, the device will degrade must fast. We, then, employed this accelerated factor to get the device lifetime that we operate under normal voltage. Using this new technique, we can save 7.88 times of testing time and, therefore, we have much more economic benefit.
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