| Summary: | 碩士 === 長庚大學 === 半導體研究所 === 90 === Today’s power amplifiers are implemented in GaAs, HBT, LDMOS, and BiCMOS technologies. However, more and more communication system is fabricated in CMOS technology. For this reason, a single chip transceiver includes an integrated CMOS power amplifier. In this work, design and implementation of a power amplifier are described.
However, the implementation of a CMOS power amplifier suffers from many disadvantages of intrinsic CMOS characteristics. Therefore, we have to introduce a different approach from the standard way which is used to design GaAs or bipolar power amplifier. We use TSMC 0.25 m processes with a switching Class E approach, which can achieve high efficiency. And we use a nonlinearly parasitic capacitance with hyperabrupt junction capacitance characteristics instead of linear one at the drain-to -bulk junction of practical MOS devices. A fully differential topologies are presented the problems of CMOS technology. In addition, a low insertion, 180 hybrid is implemented with microstrip line.
In the simulation results, we obtain the output power is 20.48 dBm, and the efficiency is 30% with input power of 16dBm.Because of some implement errors, the measurement results have some mismatch and will be illustrated.
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