| Summary: | 碩士 === 長庚大學 === 半導體研究所 === 90 === Flash memory is becoming the mainstream of the nonvolatile semiconductor memory cells. The characteristics of flash memory cell depend on cell structure. It is worthy to comprehensively study the cell structure related characteristics. Two major concerns of flash memory cells are performance and reliability. In general, split-gate flash memory is superior over conventional stack-gate structures in terms of performance and reliability. In this study, the SST cell is studied. The purpose of this study is to obtain the design guidelines for split-gate flash memory cell.
In this study, a two-dimensional process/device simulation system and an automatic measurement system are established. At first, we analyze the operation mechanisms of SST cell in details. Then we investigate the characteristics of the split-gate flash memory cell by two-dimensional process/device simulations, especially for the floating gate shape on the erasing characteristics. The influences of key process steps on cell performance are examined. We not only change the doping concentration, structure of device, but also study the effect of negative substrate bias on the programming efficiency. Design guidelines are obtained through the in-depth analysis. Reliability items, such as cycling endurance, stress induced low level leakage, etc., are needed to be examined further. Floating gate shape affect erasing characteristics, and impact cycling reliability. Although floating gate with sharper tip corner improves erasing efficiency, it degrades cycling reliability due to larger traps are generated in inter-poly dielectric layer.
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