New Folded Architecture for Two-Dimensional Discrete Wavelet Transform and its Chip Implementation

• Main Author: 林誠偉
• Other Authors: 張孟洲
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/18753634150956377901

碩士 === 長庚大學 === 電機工程研究所 === 90 === Wavelet transform is a very useful tool for several applications, including signal coding, signal analysis, and image compression. In this paper, we propose two new folded architectures and two scheduling algorithms for computing 2-D discrete wavelet transform (DWT). The first new architecture includes three decimation filters and two storage units. The filters that we use are the polyphase decomposition technique in the Filter 1, and the coefficient folding technique in the Filter2, Filter 3. The two storage units are used to store the intermediate outputs that are generated by the three filters. The second new architecture is called modified efficient architecture (MEA) includes five decimation filters and two storage units. The filters that we use are the polyphase decomposition technique in the Filter 1, and the coefficient folding technique in the Filter2, Filter 3, Filter 4, and Filter 5. The Filter 2, Filter 3, Filter 4, and Filter 5 are computing data in parallel. The two storage units are also used to store the intermediate outputs that are generated by the five filters. The two scheduling algorithms can be chosen for your need. One is used to keep the data flow regular, and another is used to give the highest priority to scheduling (LL)J outputs.