The Improvement of a Parallel Radar System on Virtuoso
碩士 === 國立中正大學 === 資訊工程研究所 === 90 === This paper describes the performance improvement over our previous parallel implementations of digital signal processing in real-time phased array radar systems on Virtuoso. A phased array radar system processes a great amount of data in order to resp...
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ndltd-TW-090CCU003920952015-10-13T17:34:58Z http://ndltd.ncl.edu.tw/handle/63461373506421256313 The Improvement of a Parallel Radar System on Virtuoso Virtuoso平台上雷達平行處理程式效能之改進 張承新 碩士 國立中正大學 資訊工程研究所 90 This paper describes the performance improvement over our previous parallel implementations of digital signal processing in real-time phased array radar systems on Virtuoso. A phased array radar system processes a great amount of data in order to respond to the ever-changing combat environment, therefore it is vital that the system is able to process the input data and produce the results in limited time budget. As a result it is inevitable that parallel processing must be adopted into digital signal processing for performance improvements. This dissertation focus on the parallel performance improvements from a system architecture point of view. In our previous implementation floating-point data type is used to represent data. Due to the architecture and system software requirement we are unable to apply assembly code on this implementation. And as a result the performance was only satisfactory. One of the most important improvement of our new implementation is that we rewrite the program with integer data type. The new implementation delivers up to eight times of performance on a Pentek 4290 ReadyFlow system with 4 nodes than our previous version. 陳添福 2002 學位論文 ; thesis 27 en_US |
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碩士 === 國立中正大學 === 資訊工程研究所 === 90 === This paper describes the performance improvement over our previous parallel implementations of digital signal processing in real-time phased array radar systems on Virtuoso. A phased array radar system processes a great amount of data in order to respond to the ever-changing combat environment, therefore it is vital that the system is able to process the input data and produce the results in limited time budget. As a result it is inevitable that parallel processing must be adopted into digital signal processing for performance improvements. This dissertation focus on the parallel performance improvements from a system architecture point of view.
In our previous implementation floating-point data type is used to represent data. Due to the architecture and system software
requirement we are unable to apply assembly code on this implementation. And as a result the performance was only
satisfactory. One of the most important improvement of our new
implementation is that we rewrite the program with integer data type. The new implementation delivers up to eight times of performance on a Pentek 4290 ReadyFlow system with 4 nodes than our previous version.
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陳添福 |
author_facet |
陳添福 張承新 |
author |
張承新 |
spellingShingle |
張承新 The Improvement of a Parallel Radar System on Virtuoso |
author_sort |
張承新 |
title |
The Improvement of a Parallel Radar System on Virtuoso |
title_short |
The Improvement of a Parallel Radar System on Virtuoso |
title_full |
The Improvement of a Parallel Radar System on Virtuoso |
title_fullStr |
The Improvement of a Parallel Radar System on Virtuoso |
title_full_unstemmed |
The Improvement of a Parallel Radar System on Virtuoso |
title_sort |
improvement of a parallel radar system on virtuoso |
publishDate |
2002 |
url |
http://ndltd.ncl.edu.tw/handle/63461373506421256313 |
work_keys_str_mv |
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