Efficient Delay Computation Considering Temporal Information
碩士 === 國立中正大學 === 資訊工程研究所 === 90 === Identification of false (unsensitizable) paths is important in determining circuits’ delay. However, the exact conditions of deciding whether a path is true or not require both the Boolean function and timing information of nodes. To reduce the complexity, most s...
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| Format: | Others |
| Language: | zh-TW |
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2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20796846571459157403 |
| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 90 === Identification of false (unsensitizable) paths is important in determining circuits’ delay. However, the exact conditions of deciding whether a path is true or not require both the Boolean function and timing information of nodes. To reduce the complexity, most sensitization criteria examine only partial timing information and are formulated as mandatory assignments on some nodes. When those assignments cannot be simultaneously satisfied, paths under consideration are claimed as false paths. In this paper, we present sensitization conditions considering full timing requirements for a true path. Our algorithms not only can detect some additional false paths which cannot be identified by heuristic algorithms [5] but also can speed up exact algorithms because of finding additional new mandatory assignments. Our experimental results are very encouraging.
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