| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 90 === This thesis presents a novel VLSI architecture for soft output Viterbi algorithm (SOVA) based on hybrid track-back of transverse paths. For the design of Viterbi decoders, the management of survivor memory usually plays a crucial role affecting the speed and power of the entire architecture. In order to achieve very high speed of decoding, majority of SOVA designs in the past use simple register-exchange method that nevertheless suffers from both complex routing and high switching activities. In this thesis, a hybrid approach that combines both the trace-back and register exchange schemes has been applied to the design of SOVA. The resulted architecture not only exhibits better regularity due to less routing, but it can also lead to lower power consumption because of reduced switching activities. In addition, the proposed approach can also save lots of registers that are often required in common SOVA architectures for holding the current decision results in order to find out the competing paths later.
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