| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 90 === Going deeper into sub-micron geometries, designing in ever decreasing wire and circuit sizes means that contemporary designers can put more electronic components in the same space on a single chip. At the same time, SOC (System On Chip) techniques support integration of several SIPs (Silicon Intelligent Property) in a chip. This reusing the SIPs that is created by other designers may reduce the time to market for a new chip. But, the power consumption problem exists still in SOC design. This problem not only affects the stability of a chip but also limits the capability.
In this thesis, we propose two different coding schemes for address bus and data bus separately. In the address bus, we propose a PAB (Prediction Address Bus) coding scheme, which uses a prediction table to record the necessary information. And we exploit 2-bit additional bus lines to indicate 4 kinds of address transmission modes. On the other side, we also use 2-bit additional bus lines for data bus. For transfer data on the data bus, we do not care the part of sign extension and encode 4 kinds of format by the MSB (Most Significant Bit) in the rest part. For transfer instruction on the data bus, we consider 3 kinds of instruction format. For each instruction format, we define partial bus line to be unused part and use one additional bus line to display. Then, we use BI (Bus Invert) coding scheme to encode the rest part of this instruction.
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