錯誤控制編碼加密法之研究及其模(2N-1)運算之心臟收縮陣列設計

• Main Author: 吳紹瑋
• Other Authors: 盧而輝
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/33174259553746414876

博士 === 國防大學中正理工學院 === 國防科學研究所 === 90 === In the dissertation, we investigate both in the error-control-coding and the systolic circuit design of some operations modulo (2N - 1). Our researches focus on the research in an algebraic-code encryption scheme, the decoder design for triple-error-correcting binary BCH codes, and the systolic-circuit designs for addition, multiplication and square modulo (2N - 1). In this research, we first propose an algorithm using a public algebraic operation to implement a modified version of the Roa-Nam algebraic-code encryption scheme instead of using the syndrome-error table. Thus, any complex algebraic code can be used to enhance the security. Moreover, the chaining mode of the modified scheme is also discussed. With this chaining mode, the modified scheme can be implemented using a very simple algebraic code without losing any security. Then, we develop a decoding algorithm for triple-error-correcting binary BCH codes. Some properties of triple-error-correcting binary BCH codes are given for deriving a new decoding algorithm. This new decoding algorithm can directly correct each received bit. It doesn't need to know the number of errors in a received vector or temporarily invert the received bit. After that, a simple and regular hardware decoder is designed, which only contains a received buffer, three syndrome registers, four ROMs of total size 2m ’ (4m + 1) bits, some arithmetic circuits in GF(2m), and a simple control circuit. Finally, we investigate three algorithms of addition, multiplication, square modulo (2N - 1) and their systolic-circuit designs. At the same time, some other basic arithmetic circuits related to subtraction, exponentiation and division modulo (2N - 1) are also discussed. In the proposed systolic circuits for three operations modulo (2N - 1), the total propagation delays of the addition circuit are the delay summation of one XOR gate, one single register; and its latency is (N + 1) clock pulses. The total propagation delays of the multiplication circuit are the delay summation of two XOR gates, one single register; and its latency is (2N + 1) clock pulse. The total propagation delays of the square circuit are the delay summation of two XOR gates, one single register; and its latency is (e1.5Nu + 1) clock pulses.