A 2.4GHz RF CMOS Frequency Synthesizer

• Main Authors: Ming-Hui Tung, 董明輝
• Other Authors: Sau-Mou Wu
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/42354436412758075707

碩士 === 元智大學 === 電機工程研究所 === 89 === In this thesis, the relationship among linearity and noise performance of a CMOS RF Frequency Synthesizer are studied and optimized. The 2.4GHz Frequency Synthesizer is fabricated and measured. The PLL architecture is based on integer-N to construct a channel spacing range 83MHz at 2.4GHz for the ISM band. The VCO of the Frequency Synthesizer is mainly designed by planar-inductor that is suitable for RF VCO design. The operation frequency is from 2.35GHz to 2.73GHz and its phase noise is —72dBc/Hz at 100kHz, -95dBc/Hz at 600kHz and —102dBc/Hz at 1MHz offset from the carrier. The integer-N PLL synthesizer controls the frequency from 2.4GHz to 2.483GHz and the lock time is 43μs with 3.3V supply. The whole Frequency Synthesizer is fabricated in 0.35μm TSMC process. The chip area is 1 mm by 1.5 mm using TSMC1P4M CMOS process.