A 4th-Order Bandpass Sigma-Delta Modulator

• Main Authors: Chia-Hau Chang, 張家豪
• Other Authors: Sau-Mou Wu
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/53026796264779690882

碩士 === 元智大學 === 電機工程研究所 === 89 === This paper presents a 4th-order bandpass sigma-delta oversampling modulator, which can be used in the digital wireless communication receiver. It converts analog signals to the digital domain at the intermediate frequency. The modulator is implemented in the UMC 0.5μm CMOS 2p2m process with power supply ±2.5V. The bandwidth is 200kHz centered at the 5Mhz.The sample frequency is 20MHz. The peak SNR is about 65 dB. The power consumption is 179.3mW. The modulator layout area is 792um*1076um. The chip area is 1800um*1800um。