The Research of Low-Voltage Fully Differential CMOS High-Speed Sample-and-Hold Circuit
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 89 === A new technique for realizing a low-voltage fully differential CMOS high-speed sample-and-hold (S/H) circuit is presented. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The design consideration of t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53486022499442607311 |