The Design of 3 Bands CMOS Phase-Locked Loop

The Design of 3 Bands CMOS Phase-Locked Loop

碩士 === 淡江大學 === 電機工程學系 === 89 === This thesis describe a 3 bands PLL (Phase-Locked Loop), each channel have 3 channels. This PLL is implemented in UMC 0.5μm standard CMOS process. In chapter 2 of this thesis, the basic theorem and operation of Phase-Locked loop will be intr...

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Bibliographic Details
Main Authors:	Chun-Hung Lien, 連俊宏
Other Authors:	Wen-Ching Chang
Format:	Others
Language:	en_US
Published:	2001
Online Access:	http://ndltd.ncl.edu.tw/handle/28961166337826265746

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